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One of the problems in high speed computing is the limited capabilities of communication links in digital high performance electronic systems. Too slow and too few interconnects be‐ tween VLSI circuits cause a bottleneck in the communication between processor and memo‐ ry or, especially in multiprocessor systems, among the processors. Moreover, the problem is getting worse since the increasing integration density of devices like transistors leads to a higher requirement in the number of necessary channels for the off-chip communication. Hence, we are currently in a situation, which is characterized by too few off-chip links and too slow long on-chip lines, what is described as the interconnect crisis in VLSI technology [1]. More than ten years the use of optical interconnects is discussed as an alternative to solve the mentioned problems on interconnect in VLSI technology [2]. A lot of prototypes and demonstrator systems were built to prove the use of optics or optoelectronics for offchip and on-chip interconnects [3]. The possibilities of current VLSI technology would allow integrating a massively-parallel array processor consisting of a few hundred thousand sim‐ ple processor elements (PEs) on a chip. Unfortunately it would be a huge problem to ar‐ range several of such PE arrays one after the other in order to realize a highly–parallel superscalar and super-pipelined architecture as well as an efficient coupling to a memory chip. The reason for these difficulties is the not sufficient number of external interconnects to move high data volumes from and to the circuits. In optoelectronic VLSI one tries to solve limitation problem by realizing external interconnects not at the edge of a chip but with ar‐

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Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High- Performance Processing