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Analog circuits form an important part in integrated circuits and in particular in ASICs (Application Specific Integrated Circuits). However, due to the high complexity, design of this part has become a bottle-neck in the design flow (Gielen, 2007; Rutenbar et al., 2007). To overcome this problem and to guaranty that the analog part can be designed in reasonable time even for future technologies, methods supporting automatic design of analog circuits must be advanced. This chapter focuses on sizing of analog circuits. It starts from the point where a topology is given. The task now is to choose design parameters, e.g., lengths and widths of transistors, such that certain properties of the circuit are fulfilled. Current tools to solve the sizing task mostly treat it as a continuous optimization problem and use, e.g., certain gradient-based approaches to solve the problem in the continuous domain (Graeb, 2007). However, many design parameters are discrete in reality, e.g., transistor multipliers (i.e., the number of transistors connected in parallel), or must be discretized for some practical purposes, e.g., transistor lengths and widths which should match to a manufacturing grid. Furthermore, for some future technologies as, e.g., FinFETs (Knoblinger et al., 2005), the transistor parameters must fulfill certain geometrical properties, and accordingly have to be discrete. Considering discrete parameters, it is not sufficient to treat the sizing task as a continuous optimization problem and rounding the result. This can be followed from mathematical theory, where it is shown that continuous optimization with sub-sequent rounding might not solve the original discrete optimization task (i.e., a optimization task that considers discrete and continuous parameters) and leads to a suboptimal result (Li & Sun, 2006; Nemhauser & Wolsey, 1988). This can be confirmed by experiments. To solve discrete optimization problems, statistical and evolutionary approaches have been proposed (Alpaydin et al., 2003; Cao et al., 2000; Gielen et al., 1990; Ochotta et al., 1996; Phelps et al., 2000; Somani et al., 2007). However, for practical approaches these tools are usually more slowly in comparison to deterministic gradient-based tools if a good initial solution can be given for the task (what is normally true for analog sizing). Even if statistical and evolutionary approaches might be the first choice if a global search is necessary, for many cases deterministic gradient-based approaches are more suitable. Deterministic approaches for discrete sizing of analog circuits have barely been published till today (Pehl & Graeb, 2009; Pehl et al., 2008). In this chapter a new deterministic gradient-based approach is presented. It An SQP and Branch-and-Bound Based Approach for Discrete Sizing of Analog Circuits 13