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Short-distance optical communications and emerging optical storage (OS) systems increasingly require fast (i.e with Gigahertz to tens of Gigahertz bandwidth) and integrated Si photodetectors (Csutak et al., 2002; Hobenbild et al., 2003; Zimmermann, 2000). Thin-film SOI integrated devices appear as the best candidate to cope with these high-speed requirements, notably for the 10Gb/s Ethernet standard (Afzalian & Flandre, 2005; 2006.a; Csutak et al., 2002). For such bandwidths design trades-off between speed and responsivity are very severe and require a careful optimization (Afzalian & Flandre, 2006.b). In this context, accurate analytical modeling is very important for insight, rapid technology assessment for the given application, and/or rapid system design. There is however a lack of these accurate models in the literature so that time consuming devices simulations are often the only solution. In (Afzalian & Flandre, 2005), we have proposed such an accurate analytical model for the responsivity of thin-film SOI photodiodes. In here, thorough analytical modeling of AC performances of thin-film lateral SOI PIN photodiodeswill be addressed. Speed performances depend on a trade-off between transit time of carriers and a RC constant related to the photodiode and readout circuit combined impedances. We will first focus on the transit time limitation of the thin-film SOI PIN diodes (section 2). Then, we will model the complex diode impedance using an equivalent lumped circuit (section 3). For a lateral SOI PIN photodiode indeed, the usual approximation of considering only the depletion capacitance, Cd, reveals insufficient. Our original model, fully validated by Atlas 2D numerical simulations and measurements, allows for predicting and optimizing SOI PIN detectors speed performances for the target applications in function of technological constraints, in particular their intrinsic length, Li, which is their main design parameter.

Design of Thin-Film Lateral SOI PIN Photodiodes with up to Tens of GHz Bandwidth