English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Modern system designs become more and more complex due to the progress of VLSI manufacturing technologies. In nanometer IC technologies and SoC (System on Chip) design flow, existing placement approaches face many serious challenges, including large size(billions of transistors), mix-size cell placement, wire congestion, and more complex design constraints (delay, noise, manufacturability, etc). Since the IC design market is more and more competitive, it is necessary to have faster time to market, smaller silicon area utilization, and less wire length for layout. Efficient and effective design methodologies of large scale design placement are essential for modern SoC designs. Many placement methods have been presented in the literature (Chang et al., 2000; Guo et al., 1999; Lin C 2002a; Lin et al., 2003; Murata et al., 1995; Nakatake et al., 1996; Otten, 1982; Wong & Liu, 1986). Because of inflexibility in representing non-slicing placement and non-hierarchical data structures, the performance of traditional placement algorithms were not very good. Until recently, the B*-tree representation (Chang et al., 2000) provided an efficient, effective, and flexible data structure for non-slicing placement. Furthermore, MB*-tree algorithm (Lee et al., 2003) has presented multilevel framework which is more facilitating to solve large-scale floorplanning/placement problem. However applying simulated annealing approach in declustering stage spent much more time to search for better solutions. On the other hand, the ǫ-neighborhood and λ-exchange algorithm, first presented in (Goto, 1981) and further applied in (Chan et al., 2000), was used for standard cell based placement. This method, for permuting cells with wire length driven approach, gave better performance compared with randomly interchanges of cells in simulated annealing paradigm. This limited trial permutation enable us to find a good local optimum solution more efficiently. The challenge lies in the modification of this approach to large-scale modules placement. In this work, we transform the ǫ-neighborhood and λ-exchange to fit in the large-scale modules placement and use it in the refinement stage of MB*-tree algorithm. This method searches the solutions in thewhole permutation of the selectedmodules. Although our ǫ-neighborhood and λ-exchange approach takes much time for one perturbation, its efficiency will compensate for the computation time by comparing with randomly interchanges, and more efficient in general compared with original MB*-tree. The results are encouraging. We have obtained 13

Multilevel Large-Scale Modules Floorplanning/Placement with Improved Neighborhood Exchange in Simulated Annealing