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In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is . S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process