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Embedded Systems play an important role on today's interconnected world. However, there is a gap in relation to Verification and Validation (VV ii) the Failure Mode and Effects Analysis (FMEA); and iii) the syntactic and semantic elements available in the formalism of the SysML language. A feasibility study was carried out to evaluate the effectiveness and efficiency of one of the techniques. From a total of 26 subjects, 50% have found an average of 72% of defects and spent an average of 48 minutes.

Verification and Validation Activities for Embedded Systems - A Feasibility Study on a Reading Technique for SysML Models