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. An attractive solution to provide several channels with very high data ratesof tens of Gbit s −1 for digital-to-analog converters (DACs) in arbitrarywaveform generators (AWGs) is to use a high speed serializer in front of theDAC. As data sources, on-chip memories, digital signal processors orfield-programmable gate arrays can be used. Here, we present a serializerconsisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to64 Gbit s −1 per channel and a low skew ( ∼  8.8  ps )two-phase frequency divider and clock distribution network that is completelyrealized in static CMOS logic. The circuit is designed in a 28  nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used inan 8  bit 64 GS s −1 DAC between the on-chip memory and the DACoutput stage. Due to a four bits unary and four bits binary segmentation, a19 channel MUX is required. Simulations on layout level reveal adata-dependent peak-to-peak jitter of less than 1.8  ps at the outputof one MUX channel with a total average power consumption of approximately1.15  W of the whole MUX and clock network.

advances in radio science

High-Speed Serializer for a 64 GS s&amp;lt;sup&amp;gt;−1&amp;lt;/sup&amp;gt; Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology