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This paper reports on an effective root-cause analysis\udmethod of memory effects in power amplifiers, as well as introduces\udcompensation techniques on a circuit design level. Despite conventional\udmemory-effect approaches, the discussed method uses a two-tone scan over a\udwide operation and modulation range. This enables an in-depth study of\udphysical causes and helps to implement compensation techniques at design\udstage. On the one hand, this circuit investigation is optimized using an\udautomated SystemC model parametrized with real device and measurement\udvalues. Hence, computation time is widely reduced which shortens design\udcycles. On the other hand, the implementation of the derived circuit\udcompensation means will reduce the complexity of digital pre-distortion due\udto a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach\udis demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a\udPAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be\udreduced by more than 8 %

Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation