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This paper presents a numerical comparison of charge pumps (CP) designed fora high linearity and a low noise to be used in a fractional-N phase-lockedloop (PLL). We consider a PLL architecture, where two parallel CPs with DCoffset are used. The CP for VCO fine tuning is biased at the output to keepthe VCO gain constant. For this specific architecture, only one transistorper CP is relevant for phase detector linearity. This can be an nMOSFET, apMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows thehighest linearity, whereas all charge pumps show similar device noise. Aninternal supply regulator with low intrinsic device noise is included in thedesign optimization

Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs