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High-speed imaging is one of the key methods in a wide range of applications to understand basic physical processes. In traditional high-speed imaging a certain number of images is taken and stored in a high-speed memory directly attached to the image sensor of the imaging device. However the size of this memory limits the number of frames or the image size which can be capture. In this proposal a real-time processing of image data on a reconfigurable logic device, which is directly connected to the image sensor is proposed. This architecture is able to process a very high-speed pixel stream without the need of storing full images at all and is able to extract object feature in real-time. The proposed FPGA image processing architecture uses a combination of two recently proposed single pass algorithm for the task of feature extraction and is able to process up to several 1000 frames per second.

C5.3 - Imaging Sensor with Integrated Feature Extraction Using Connected Component Labeling