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Due to the fact that, the power consumption and speed of a VLSI circuit are dependent on the transistor sizes, efficient transistor sizing is a new challenge for VLSI circuit designers. However, evolutionary computation can be successfully used for complex VLSI transistor sizing which reduces the time to market and enables the designer to find the optimized solutions for a non-linear and complex circuit design process. In this paper, a new digital integrated circuit design approach is proposed based on the firefly artificial intelligence optimization algorithm. In order to justify the effectiveness of the proposed algorithm in the design of VLSI circuits, an inverter (NOT gate) is designed and optimized by the proposed algorithm. As the simulation results show, the inverter circuit has a very good performance for power and delay parameters.

A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm