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Full Adder is one of the critical parts of logical and arithmetic units. So,presenting a low power full adder cell reduces the power consumption of theentire circuit. Also, using Nano-scale transistors, because of their uniquecharacteristics will save energy consumption and decrease the chip area. Inthis paper we presented a low power full adder cell by using carbon nanotubefield effect transistors (CNTFETs). Simulation results were carried out usingHSPICE based on the CNTFET model in 32 nanometer technology in Different valuesof temperature and VDD.

Energy Efficient Full Adder Cell Design With Using Carbon Nanotube Field Effect Transistors In 32 Nanometer Technology