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In this paper average power consumption, write access time, read access time and retention time of dram cell designs have been analyzed for the nano-meter scale memories. Many modern day processors use dram cell for on chip data and program memory storage. The major power in dram is the off state leakage current. Improving on the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designed with the schematic design technique and their average power consumption are compared using TANNER EDA tool .average power consumption, write access time, read access time and retention time of 4T, 3T dram and 3T1D DRAM cell are simulated and compared on 32 nm technology.

Design and Implementation of 4T, 3T and 3T1D DRAM Cell Design on 32 NM Technology