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The Digital Image processing applications like medi\udcal imaging, satellite imaging, Biometric trait ima\udges \udetc.,  rely  on  multipliers  to  improve  the  quality  of\ud  image.  However,  existing  multiplication  techniques\udintroduce errors in the output with consumption of \udmore time, hence error free high speed multipliers \udhas \udto  be  designed.  In  this  paper  we  propose  FPGA  based\ud  Recursive  Error  Free  Mitchell  Log  Multiplier \ud(REFMLM)  for  image  Filters.  The  2x2  error  free  Mitc\udhell  log  multiplier  is  designed  with  zero  error  by \udintroducing   error   correction   term   is   used   in   higher\ud   order   Karastuba-Ofman   Multiplier   (KOM) \udArchitectures.  The  higher  order  KOM  multipliers  is \uddecomposed  into  number  of  lower  order  multipliers \udusing radix 2 till basic multiplier block of order \ud2x2 which is designed by error free Mitchell log mu\udltiplier. \udThe  8x8  REFMLM  is  tested  for  Gaussian  filter  to  rem\udove  noise  in  fingerprint  image.  The  Multiplier  is \udsynthesized  using  Spartan  3  FPGA  family  device  XC3S\ud1500-5fg320.  It  is  observed  that  the  performance \udparameters such as area utilization, speed, error a\udnd PSNR are better in the case of proposed architec\udture \udcompared to existing architecture

FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture