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Today, all the portable device’s in electronics needs to be realized with low power architectures because ofpower consumption is a main consideration along with other performance parameters. Low powerconsumption helps to reduce heat dissipation, increases battery life and also reliability. In this paper a 16-bit Reduced Instruction set Architecture (RISA) presented. This architecture can handle multiple interruptsand performing serial communication effectively. It can supported RISC (Reduced Instruction SetComputer) concepts. A popular technique of Clock gating is applied to the proposed architecture and thenreduces the power. This entire architecture captured using VerilogHDL and implemented on FPGA usingXilinx tools

Low Power Reduced Instruction Set Architecture Using Clock Gating Technique