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In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations .

international journal of vlsi design and communication systems

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance