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Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints.This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression sequence like BPSk, QPSk, 6-PSKand other Poly phase codes. The VLSI architecture is implemented on the Field Programmable Gate Array(FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.\u

Area Optimized FPGA Implementation for Generation of Radar Pulse Compression Sequences