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Today every circuit has to face the power consumption issue for both portabledevice aiming at large battery life and high end circuits avoiding coolingpackages and reliability issues that are too complex. It is generally acceptedthat during logic synthesis power tracks well with area. This means that alarger design will generally consume more power. The multiplier is an importantkernel of digital signal processors. Because of the circuit complexity, thepower consumption and area are the two important design considerations of themultiplier. In this paper a low power low area architecture for the shift andadd multiplier is proposed. For getting the low power low area architecture,the modifications made to the conventional architecture consist of thereduction in switching activities of the major blocks of the multiplier, whichincludes the reduction in switching activity of the adder and counter. Thisarchitecture avoids the shifting of the multiplier register. The simulationresult for 8 bit multipliers shows that the proposed low power architecturelowers the total power consumption by 35.25% and area by 52.72 % when comparedto the conventional architecture. Also the reduction in power consumptionincreases with the increase in bit width.

international journal of computer science and information technology/international journal of computer science and information technology  (chennai. print)

Low Power Shift and Add Multiplier Design