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Formal verification is one of the crucial stages of design phase that ensure the preciseness of the circuit design and its corresponding behavior with respect to specific system design. From last decade, there has been an abundant formal verification techniques introduced by the research community for analog and mixed signal circuits that used as an interface between analog and digital components. Owing to the maximized sophistication, and shrinking sizes of chip, analog, and mixed signal verification is encountering challenges in increasing verification requirement that calls for analyzing the prior techniques. The prime purpose of this paper is to discuss the most standard models, and techniques introduced till date and to excavate the various facts about their effectiveness in the area circuit design principles. The paper also discusses some of the critical research gaps explored from the study.

Research Trends in Formal Verification Process for Analog and Mixed Signal Design