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Power dissipation has become one of the major concerns of VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, an 8X8 multiplier is designed using different leakage power reduction techniques like MTCMOS, DUAL-V t and LECTOR. All the above mentioned techniques are simulated using Cadence virtuoso tool in 90nm technology. Keywords 8X8 multiplier, MTCMOS, DUAL-V t , LECTOR, Proposed methods 1. INTRODUCTION The rapid increase in semiconductor technology led the feature sizes to be shrinking by using deep-submicron processes. System on a chip (SoC) is an integrated circuit that integrates complex functions on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. With miniaturization and the growing trend towards wireless communication, power dissipation has become a very critical design metric. The longer the battery lasts, the better is the device. With the advancement in technology, static power dominates dynamic power. Leakage currents are especially important in burst mode type integrated circuits where most of the time the system is in an idle, or sleep mode. No computation takes place during sleep mode [1]. For example, a cell phone will be in the standby mode for most of the time where the processor is in idle state. With the large leakage currents during the idle mode power will be continuously drained with no useful work being done. Many techniques have been proposed [2] to minimize these leakage currents in nanometer technology. Excessive power dissipation in portable devices causes overheating, reduces chip life, functionality and degrades performance. Minimizing power consumption is therefore important and necessary, both for increasing levels of integration and to improve reliability, feasibility and cost.

Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design