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In today’s techno-savvy world the need of the hour is to develop devices which are power efficient as well as occupy very less area. VLSI circuits have proved to be the vital choice for most of the design engineers in order to reduce power consumption in any device. The most basic operation in any processor circuitry involves addition. Carry Select Adder (CSA) is a high speed adder and its structure reveals that there exists a possibility of reducing area and power dissipation of the circuit. This paper presents power and delay analysis of 16-Bit Square Root CSA implemented through Hybrid PTL/CMOS logic .It examines the performance of the proposed design in terms of area, delay, power in 90nm CMOS process technology. The result shows that proposed Square Root CSA structure is better in terms of area, power and Power Delay Product (PDP) than others.

Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic