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In the present works, mainly power consumption of circuit is main issue for every designers. This paper mainly dealing with the implementation of CMOS Charge sharing latch Comparator and analysis of it using different parameter in 90nm.For the implementation of new design the features of two important Comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two Comparator are Resistive Dividing Comparator and Differential Current sensing respectively. The simulation result is shown in 90nm technologies, for 2.4GHz clocked comparator by using 0.9V input. Again the result of 90nm technology is compared with 180nm technology to show the reduction of power and enhancement of speed. The implementation is done on the Cadence virtuoso design environment. Keyword: Power analysis, CMOS latch comparators.

Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology