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The propagation delay of a logic signal through a through silicon via (TSV) in a 3D IC may depend on a soft open defect inside it. The propagation delay of a defective TSV which is connected only with barrier metal, in part owing to a soft open defect, is analyzed with an electromagnetic simulator and a circuit one in this paper. The results reveal that if such a soft open defect occurs inside a TSV, the delay depends on the defect size and the IC may work without any errors. A soft open defect will change into a hard open one in operation of a 3D IC and may generate a logical error. In order to realize high reliability of the IC, the defect should be detected before it changes into a hard open defect. In this paper, test input vectors are proposed with which a soft open defect can be detected by delay testing. However, the simulation results suggest that when the input and output capacitance of a TSV is small, the defect may not be detected even if the test vectors are provided to the defective IC, since the propagation delay of the defective TSV can be smaller than a defect-free one.

Propagation Delay Analysis of a Soft Open Defect inside a TSV