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We have established a plating condition which shortens the plating time for through-electrode silicon vias with 10 μm diameters and 70 μm depths within an 8-inch wafer from 90min to 60min. We evaluated the microstructures after annealing as a function of plating conditions. It is found that the grain size of the plating films formed with conventional, i.e., high-pulse current density and low-duty cycle pulse conditions, are smaller than those for high-speed solution flow plating films. We also showed clearly that the diamond pyramid hardness number (Hv) of through-electrode Cu plating films is proportional to the square of the reciprocal of the grain size (d).

Reduction of Plating Time for Through Silicon Via (TSV) by High-Speed Solution Flow Plating Method and Texture Investigation of the TSV