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実装応力に起因した半導体デバイスの電気特性変動について, 応力効果を考慮したデバイスシミュレーションによる評価を行った。その際, ゲート長さが異なる3種類(ゲート長さ24μm, 0.8μm, 85 nm)のnMOSFETに対して, デバイス内部の微細構造に起因する応力分布の影響を考慮した。DC特性値の変動をシミュレーションした結果, デバイス内部の応力分布を考慮した場合の変動率の方が, 公称応力値(チップ表面の応力値)に対する変動率よりも小さくなった。デバイスの微細構造に起因するチャネル領域の残留応力が, デバイスの電気特性に有意な影響を及ぼすことを示した。Packaging-induced variations on the electrical characteristics of semiconductor devices were evaluated using a device simulation. The electrical characteristics of nMOSFETs with 24μm, 0.8μm and 85 nm gate lengths were simulated, and the effects of the stress distribution generated by the microstructures of the devices were evaluated in this simulation. The results show that, under the nominal stress, the variations in the DC characteristics were similar between all of the nMOSFET types. On the other hand, the variations in DC characteristics under the stress distribution obtained by a FEA were smaller than those under the nominal stress. The device simulation results demonstrated that the stress distribution induced by the microstructure of the device affected the electrical characteristics of the devices

Device Simulation of Packaging-Stress Effects of Semiconductor Devices: Evaluation of the Impact of Stress Distribution in the Devices