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In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication  in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular  reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate  the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel  linear feedback registers. The new algorithm is described in detail and results from a hardware implementation  on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6  device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted  finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed  multiplier uses 36% less area resources and improves the maximum delay in 10%

Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)