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<div>The growing size and complexity of VLSI circuits have made quality and reliability requirements increasingly stringent. The work presented in this paper investigates the application of Boolean Satisfiability (SAT)-based techniques to address two distinct VLSI testing activities, namely, test vector generation to excite stuck-open faults in CMOS circuits, and test vector generation for dynamic burn-in testing. The presence of a stuck-open fault renders an otherwise combinational logic gate sequential, therefore causing a malfunction of the integrated circuit. On the other hand, burn-in screening has been an integral part of semiconductors manufacturing to assure that reliability goals are achieved. The purpose of this type of testing is to apply to the device under test a set of input patterns which maximizes the circuits nodal activity, and by so doing causing an increase in its power dissipation that leads to device failures like electromigration and hot-carrier degradation at an early stage of the device operation.</div><div> </div><div>The search for input or test patterns to either excite a stuck open fault, or to maximize the activity in the circuit is an NP-complete problem. In this work, we discuss the applicability of</div><div>SAT methodologies in tackling these two testing problems. We</div><div>experiment with SAT and Integer Linear Programming (ILP)</div><div>solvers to compute solution sets for these two testing activities.</div

Using SAT-Based Techniques in Test Vectors Generation