English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

This paper presents area efficient architecture of modulo 2n - 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2n - 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log2n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.

Area Efficient Sparse Modulo 2&lt;sup&gt;n&lt;/sup&gt; - 3 Adder

Area Efficient Sparse Modulo 2<sup>n</sup> - 3 Adder