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This artifact provides the means for reproducing the experiments presented in the paper “Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoC”. In particular, it provides the means and describes how to replicate the experimental study that has been carried out to evaluate the proposed analysis with synthetic workloads. 2012 ACM Subject Classification Hardware → Interconnect; Hardware → Hardware accelerators

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact)