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In this paper, a Flexible And Accurate Network-On-chip Simulator (FAANOS) is introduced. NoC is a critical structure for system-on-chip design. We discuss the structure of its various components by presenting their details. We also provide an analytical methodology that employs the micro-architectural level of routers and links of NoC by considering their power and chip area requirements. We go through the structure of FAANOS when it is in switching mode and explain the transactional power estimation metric. To evaluate the effectiveness of an NoC system, an evaluation flow for early stage design and simulation of NoC is presented.

Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation