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Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs
Author(s) -
Maryam Murad,
Ishfaq Hussain,
Ayaz Ahmad,
Muhammad Yasir Qadri,
Nadia N. Qadri
Publication year - 2019
Publication title -
turkish journal of electrical engineering and computer sciences
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.225
H-Index - 30
eISSN - 1303-6203
pISSN - 1300-0632
DOI - 10.3906/elk-1812-59
Subject(s) - design space exploration , benchmark (surveying) , computer science , throughput , mathematical optimization , multi objective optimization , energy consumption , estimation of distribution algorithm , maximization , genetic algorithm , evolutionary algorithm , cache , reduction (mathematics) , algorithm , parallel computing , mathematics , embedded system , wireless , engineering , geometry , geodesy , electrical engineering , telecommunications , geography
Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain. The exploration of design space for finding the best power–throughput trade-off is a combinatorial optimization problem with a large number of combinations, and. in general, its solution is prohibitively difficult to be explored exhaustively. However, fortunately, evolutionary algorithms (EAs) have the potential to efficiently solve this problem with reasonable computational complexity. In this paper, we consider a multiobjective design space exploration (DSE) problem with two conflicting objectives. The first objective corresponds to power consumption minimization while the second objective relates to throughput maximization. We approach this problem by employing the estimation of distribution algorithm (EDA), which belongs to the family of EAs. The proposed EDA-based DSE (EDA-DSE) scheme efficiently selects the design parameters (i.e. cache size, number of cores, and operating frequency) with an efficient power–throughput ratio. The proposed scheme is verified using cycle-accurate simulations over a set of benchmarks and the simulation results show a significant reduction in energy-delay product for all benchmark applications when compared to the default baseline configuration and genetic algorithm.

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