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At submicron manufacturing technology nodes process variations affect circuitperformance significantly. This trend leads to a large timing margin and thusoverdesign to maintain yield. To combat this pessimism, post-silicon clocktuning buffers can be inserted into circuits to balance timing budgets ofcritical paths with their neighbors. After manufacturing, these clock bufferscan be configured for each chip individually so that chips with timing failuresmay be rescued to improve yield. In this paper, we propose a sampling-basedmethod to determine the proper locations of these buffers. The goal of thisbuffer insertion is to reduce the number of buffers and their ranges, whilestill maintaining a good yield improvement. Experimental results demonstratethat our algorithm can achieve a significant yield improvement (up to 35%) withonly a small number of buffers.

Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability