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Problem statement: The development cost for Application Specific Integrated Circuits&#13; (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital&#13; Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication.&#13; The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA)&#13; devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and&#13; Virtex-5 FPGA devices. The implementation of standard and truncated multipliers is done using Very&#13; high speed integrated circuit Hardware Description Language (VHDL). Results: Remarkable&#13; reduction in FPGA resources, delay and power was achieved using truncated multipliers instead of&#13; standard parallel multipliers when the full precision of the standard multiplier is not required. The three&#13; devices showed significant improvement for truncated multipliers as compared to standard multipliers.&#13; Results showed that the anomaly in Spartan-3AN average connection and maximum pin delay have been&#13; efficiently reduced in Virtex-4 and Virtex-5 devices. Conclusion: The Virtex-5 FPGA device showed&#13; better performance as compared to Spartan-3AN and Virtex-4 FPGA devices

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices