English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES. Keywords:Soft Error, VLIW Architecture, Instruction Duplication, Reliability, VLES, Code Size

Soft Error Detection for VLIW Architectures with a Variable Length Execution Set