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In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.Keywords:DFT, Boundary Scan, IEEE1149.1, Runtime Test 1.   1)        ,             .     IC     ,         .   IC   (Primary Input: PI) (Primary Output: PO)   (TDI)   (TDO)

Development of Continuous Capture Test Architecture in the Boundary Scan