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This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V. Keywords—Low-dropout linear regulators; CMOS analog integrated circuits; Weak inversion region; Power consumption; Negative and Positive feedback; Noise Received: August 01, 2001. Revised: September 4, 2020. Accepted: October 22, 2020. Published: October 29, 2020. WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS DOI: 10.37394/23201.2020.19.34 Hicham Akhamal, Mostafa Chakir, Hatim Ameziane, Mohammed Akhamal, Kamal Zared, Hassan Qjidaa E-ISSN: 2224-266X 311 Volume 19, 2020 different techniques have been proposed in the literature to improve the transient response of LDOs. In [5]-[8] a reduced supply voltage is necessary to decrease power consumption to ensure a reasonable battery lifetime in portable electronics. For the same reason, low-power circuits are also expected to reduce thermal dissipation, of increasing importance with the general trend in miniaturization. In [2]-[3], current amplifier Miller compensation is used, reducing the total compensation capacitance but increasing the power consumption and the complexity of the design. Furthermore, in [9]-[13], Gm-C filters are employed to omit offset and noise signals, but the drawback of these circuits is their high power dissipation. Even in [1], if the resistors of these amplifiers are implemented using transistors, its power consumption is still a problem. In addition, a cascode compensation with a dynamic bandwidth boosting was proposed in [12]-[16], which guaranteed stability over the full range of alternating load current at the expense of high power consumption. Hence, to ensure stability, frequency compensation is always required especially for multistage amplifiers. For this reason, some frequency-compensation topologies such as nested miller compensation [13] have been used to implement multistage amplifiers. In these amplifiers, although the stability problem has been basically solved, the enormous power dissipation and bandwidth reduction remain a serious problem. Unfortunately, the problem of the energy consumption still exists. Although these topologies can basically solve the problem and make multistage amplifiers practicable, they suffer from serious problems such as enormous power dissipation and bandwidth reduction. More importantly, existing structures of the regulators operate in the region of strong inversion static dissipating a power of a few microwatts. Particularly, the optimization of the power dissipated in these circuits is the subject of study for many designers. The classics regulators CMOS operating in the strong inversion region [25]-[26], the design of these circuits is made with polarized transistors in the region of strong inversion of the drain-source channel [25]. In this region, the gatesource polarization voltage VGS is greater than the conduction threshold voltage VTH (│VGS│> │VTH│) hence the drain current of a few microamperes and therefore the power dissipated in the regulator is a few microwatts. In this paper, we propose a new regulator LDO structure operating in the weak inversion region, the static power dissipated in the regulator is thus reduced of some nano-watts. In the recent years, the increasing demand of these circuits, consequently, push the designers to improving the performance. Our study is busy at the minimization of the static power (quiescent power) dissipated in the regulators. The basic idea is to polarize all transistors that are enter in the design of the regulator (except the pass transistor: power transistor) with the currents drains of a few nano-amperes in the weak inversion region of the transistors. In this region, the gates-source voltages│VGS│are slightly lower than the conduction threshold voltage│VTH│ (│VGS│<│VTH│). The power dissipated in the regulator is thus greatly reduced. The small Slew-rate of the output error amplifier signal (pnincipal blocks of the regulator) is the major drawback of the regulators operating in the weak inversion region. The basic idea of the solution to this problem is to amplify by mirror effect the low current polarization of the amplifier. So the load capacitor the latter is controlled by an output current of a few nanoamperes error, the process allows to get a slew-rate of the same order of the grandeur as that of the amplifier operating in strong inversion. 2. Proposed LDO Architecture The proposed LDO regulator is depicted in Fig 1. The error amplifier is realized by a dynamically biased differential amplifier input stage with transistors NMOS-PMOS. Moreover, for good performance at: low power dissipation, low frequencies, the output stage is controlled by a feedback loop. This feedback loop consists of an amplifier driving the gate of transistor MP, So the gate of transistor MP has to be driven at a gate-source voltage than the output voltage and this might be lower than the input voltage of the LDO. The feedback network (FB) is realized by four diodeconnected PMOS transistors, M1, M2, M3 and M4, with same aspect ratio. By using this approach, the silicon area of the feedback network is smaller as compared to the conventional approach using passive resistors. The reference voltage, VREF, is half of the LDO regulator output voltage. Sub-threshold MOS transistors are utilized as a feedback network instead of conventional poly or N-well resistors in order to save standby current, minimize power dissipation and minimize silicon area. Indeed, the band-gap current drained through the pass transistors provide WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS DOI: 10.37394/23201.2020.19.34 Hicham Akhamal, Mostafa Chakir, Hatim Ameziane, Mohammed Akhamal, Kamal Zared, Hassan Qjidaa E-ISSN: 2224-266X 312 Volume 19, 2020 enough phase margin to guarantee stability, even at no load condition [6]. The transistor MP is sub-power and main power transistor. The transistor size of MP is 600μm/100nm. The feedback network is realized by a string of diode-connected PMOS transistors M29 M34 biased in the sub-threshold region to minimize quiescent current as well as the silicon area [14]. Furthermore, in ultra-low power design, the silicon area will be much larger if the feedback network is realized by conventional approach using passive resistors [00]-[00]. Finally, the error amplifier was implemented using two-stage with self biased current mirrors topology. Note that the transistors M3, M4, M9, M10, M11 and M12 are set to operate in common-gate configuration and weak inversion. A significant disadvantage of the weak inversion is that very small currents are available to drive output capacitance so the slew rate becomes very small. Therefore, a conventional common-source differential-input amplifier with small tail-current is chosen as the first gain stage, which is constructed with transistors, M1, M2, M3 and M4, and M5 acted as a tail-current. The error amplifier gain is increased with a positive feedback current mirror and a negative feedback loop. MN14, MN13, MN2, MP4 and MP9 are organized as the positive feedback current mirror. Transistors, M11, M12, M23 and M22, make up the second gain stage. Indeed, the band-gap current drained through the pass transistors provide enough phase margin to guarantee stability, even at no load condition [6]. Fig 1. Conceptual schematic of the proposed LDO 2.1. Sub-threshold Operation The MOS transistor has two primary regions of operation in which current flows from the source to the drain; they are the weak inversion or subthreshold region and the strong inversion region. The sub-threshold region occurs when the gate voltage VGS is less than the threshold voltage VT and the strong inversion region occurs when the gate voltage is greater than the threshold voltage. The subthreshold current is diffusion current and the strong inversion current is a drift current. The immediate region where the strong inversion and sub-threshold regions meet is called the transition region. Fig 2 where the drain current versus the gate voltage is represented shows the three regions. The current is plotted on a logarithmic scale so that the diffusion current, which depends exponentially on the gate voltage, can be viewed. Most nano-power amplifiers use transistors in the sub-threshold region, the subthreshold characteristics. Fig 2. Characteristics of the transistor in the weak inversion region In weak inversion regime the expression of drainsource current of the simplified model of the transistor is: ID = μn Cox W L ⁄ i (n − 1) VT 2 exp ( (Vgsi – VTH) n VT ⁄ ) (1 − exp ( − Vdsi VT ⁄ )) (1) Where W and L are the effective channel width and the effective channel length respectively, VTH is the threshold voltage, VT is the thermal voltage of the MOSFET devices, μ is the carrier mobility, and COX is the gate-oxide capacitance. The power dissipation of the proposed LDO topology is given by (2). Finally, n is a non-ideal factor known as the subthreshold slope is given by (3). WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS DOI: 10.37394/23201.2020.19.34 Hicham Akhamal, Mostafa Chakir, Hatim Ameziane, Mohammed Akhamal, Kamal Zared, Hassan Qjidaa E-ISSN: 2224-266X 313 Volume 19, 2020 Powerdiss = ( VDD

A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications