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Synthesis of the vertically aligned carbon nanotubes (CNTs) using complementary metal-oxide-semiconductor (CMOS)-compatible methods is essential to integrate the CNT contact and interconnect to nanoscale devices and ultra-dense integrated nanoelectronics. However, the synthesis of high-density CNT array at low-temperature remains a challenging task. The advances in the low-temperature synthesis of high-density vertical CNT structures using CMOS-compatible methods are reviewed. Primarily, recent works on theoretical simulations and experimental characterizations of CNT growth emphasized the critical roles of catalyst design in reducing synthesis temperature and increasing CNT density. In particular, the approach of using multilayer catalyst film to generate the alloyed catalyst nanoparticle was found competent to improve the active catalyst nanoparticle formation and reduce the CNT growth temperature. With the multilayer catalyst, CNT arrays were directly grown on metals, oxides, and 2D materials. Moreover, the relations among the catalyst film thickness, CNT diameter, and wall number were surveyed, which provided potential strategies to control the tube density and the wall density of synthesized CNT array.

Synthesis of Vertical Carbon Nanotube Interconnect Structures Using CMOS-Compatible Catalysts