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An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance–voltage technique is proposed. First, an accurate high-frequency capacitance–voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance–voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.

Extraction of Interface-Trap Densities of the Stacked Bonding Structure in 3D Integration Using High-Frequency Capacitance-Voltage Technique