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In 3D-system packaging technologies, eutectic bonding is the key technology of multilayer chip stacking and vertical interconnection. Optimized from the aspects of the thickness of the electroplated metal layer, the pretreatment of the wafer surface removes the oxide layer, the mutual alignment between the wafers, the temperature of the wafer bonding, the uniformity of pressure and the deviation of the bonding process. Under the pretreatment conditions of plasma treatment and citric acid cleaning, no oxide layer was obtained on the metal surface. Cu/Sn bumps bonded under the condition of 0.135 Mpa, temperature of 280 °C, Sn thickness of 3-4 μm and a Cu-thickness of five micrometers. Bonded push crystal strength ≥18 kg/cm 2 , the average contact resistance of the bonding interface is about 3.35 mΩ, and the bonding yield is 100%. All performance indicators meet and exceed the industry standards.

Research of Wafer Level Bonding Process Based on Cu–Sn Eutectic