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In this paper, the performance of an analog PIλ    Dμcontroller is done for speed regulation of a DC motor. The circuits for the fractional integrator and differentiator of PIλ    Dμcontroller are designed by optimal pole-zero interlacing algorithm. The performance of the controller is compared with another PIλ    Dμcontroller—in which the fractional integrator circuit employs a solid-state fractional capacitor. It can be verified from the results that using PIλ    Dμcontrollers, the speed response of the DC motor has improved with reduction in settling time (    T s    ), steady state error (SS error) and % overshoot (%M p    ).

Hardware Implementation and Performance Study of Analog PIλDμ Controllers on DC Motor