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Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.

Methodology for Digital Synthesis of Deterministic and Random Jitter Generation on Rising or Falling Edges of Data Pattern