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Triggerless Data Acquisition Systems (DAQs) require transmitting the datastream from multiple links to the processing node. The short input data wordsmust be concentrated and packed into the longer bit vectors the outputinterface (e.g., PCI Express) uses. In that process, the unneeded data must beeliminated, and a dense stream of useful DAQ data must be created.Additionally, the time order of the data should be preserved. This paperpresents a new solution using the Baseline Network with Reversed Outputs (BNRO)for high-speed data routing. A thorough analysis of the network's operationenabled increased scalability compared to the previously published concentratorbased on an 8x8 network. The solution may be scaled by adding additional layersto the BNRO network while minimizing resource consumption. Simulations weredone for 4 and 5 layers (16 and 32 inputs). The FPGA implementation and testsin the actual hardware have been successfully performed for 16 inputs. Thepipeline registers may be added in each layer independently, shortening thecritical path and increasing the maximum acceptable clock frequency.

Scalable data concentrator with baseline interconnection network for triggerless data acquisition systems