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In this paper, a novel 1200 V SiC trench MOSFET with a laterally widened P-shield region (LW-MOSFET) is presented by using the two-dimensional numerical simulation. Compared with the conventional trench MOSFET (CT-MOSFET), the LW-MOSFET demonstrates an effective enhancement on the short-circuit (SC) reliability and the optimization of static performance simultaneously. According to the simulation results, the SC withstand time (SCWT) of the LW-MOSFET at 600 V DC bus voltage can reach 8 μs, while that of the CT-MOSFET is only 3 μs at the same conditions. The main reason is that the laterally widened P-shield region can help to suppress the saturation current and mitigate the huge current accumulation near the trench area, leading to an enhancement of the SC reliability. Moreover, the Baliga’s FOM of the proposed structure is improved by 45.7%, which benefits from the higher breakdown voltage (BV) and the lower specific on-state resistance (Ron, sp) by using the optimized structure. The advantage of static performance is related to the local charge balance behavior provided by the laterally widened P-shield region, which helps to use a higher doped current spread layer (CSL) without bringing a degeneration of BV.

A 1200 V SiC Trench MOSFET with a Laterally Widened P-Shield Region to Enhance the Short-Circuit Ruggedness