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An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior