English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

Kerf-less removal of surface layers of photovoltaic materials including silicon is an emerging technology by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material; then, the controlled removal of a continuous surface layer can be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer, introducing a crack near the edge of the substrate, and mechanically guiding the crack as a single fracture front across the surface. However, spalling Si(100) at 300 K (room temperature RT) introduced many cracks and rough regions within the spalled layer. These mechanical issues make it difficult to process these layers of Si(100) for PV, and in other advanced applications, Si does not undergo phase transformations at 77 K (Liquid Nitrogen Temperature, LNT); based on this fact, spalling of Si(100) has been carried out. Spalling of Si(100) at LNT improved material quality for further designed applications. Mechanical flexibility is achieved by employing controlled spalling technology, enabling the large-area transfer of ultrathin body silicon devices to a plastic substrate at room temperature.

Crystalline Silicon Spalling as a Direct Application of Temperature Effect on Semiconductors’ Indentation