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The use of a doped Ceria buffer layer and Physical Vapour Deposition (PVD) techniques for Solid Oxide Fuel Cells (SOFC) fabrication can limit the former, the formation of electrical insulating lanthanum, and strontium zirconates at the cathode/electrolyte interface, whereas the latter allows a better control of the materials interfaces. These effects allow for operation at intermediate temperature ranges. In this work, we study the structural and electrical properties of Gadolinium Doped Ceria (GDC) barrier layer deposited via the room temperature RF Sputtering technique on anode supported electrolytes and then annealed at high temperature. The crystal structure and the surface morphology of the GDC barrier layers have been analyzed and optimized varying the temperature ramp of the post-growth annealing procedure. The electrical behavior of the obtained samples has been investigated by Electrochemical Impedance Spectroscopy and compared to that of standard SOFC with screen-printed GDC barrier layers, the former showing a maximum high frequency and low frequency resistances reduction of about 50% and 46%, respectively, with respect to the latter at an operating temperature of 650 °C. The results clearly show an important improvement of SOFC performances when using sputter deposited GDC layers, linking the electrical properties to the structural and stoichiometric ones.

catalysts

Structural and Electrical Characterization of Sputter-Deposited Gd0.1Ce0.9O2−δ Thin Buffer Layers at the Y-Stabilized Zirconia Electrolyte Interface for IT-Solid Oxide Cells