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In this review, some major aspects of the current underfill technologies for flip-chip (FC) and fine-pitch-ball-grid-array (FPBGA), including chip-size packaging (CSP), are addressed, with an emphasis on applications, such as aerospace electronics, for which high reliability level is imperative. The following aspects of the FC and FPGGA technologies are considered: attributes of the FC and FPBGA structures and technologies; underfill-induced stresses; the roles of the glass transition temperature (Tg) of the underfill materials; some major attributes of the lead-free solder systems with underfill; reliability-related issues; thermal fatigue of the underfilled solder joints; warpage-related issues; attributes of accelerated life testing of solder joint interconnections with underfills; and predictive modeling, both finite-element-analysis (FEA)-based and analytical (“mathematical”). It is concluded particularly that the application of the quantitative assessments of the effect of the fabrication techniques on the reliability of solder materials, when high reliability is imperative, is critical and that all the three types of research tools that an aerospace reliability engineer has at his/her disposal, should be pursued, when appropriate and possible: experimental/testing, finite-element-analysis(FEA) simulations, and the “old-fashioned” analytical (“mathematical”) modeling. These two modeling techniques are based on different assumptions, and if the computed data obtained using these techniques result in the close output information, then there is a good reason to believe that this information is both accurate and trustworthy. This effort is particularly important for high-reliability FC and FPBGA applications, such as aerospace electronics, as the aerospace IC packages become more complex, and the requirements for their failure-free operations become more stringent.

Flip-Chip (FC) and Fine-Pitch-Ball-Grid-Array (FPBGA) Underfills for Application in Aerospace Electronics—Brief Review