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The architectural design of the random number generators for uniform distribution, normal distribution, exponential distribution and Rayleigh distribution using Box-Muller and inverse transformation method has been hardware implemented on FPGA. Any of the random number generators can generate one sample every clock cycle. The generators have been implemented on Xilinx Spartan 3E XC3S500E FPGA. The designed generators work properly up to maximum frequency of 418.41MHz .The outcome results of the generators have been tested by the chi-square test at a 5% level of significance which provided the correct required distributions. Keyword: Box-mulle, Chi-square, Inverse transformation, FPGA. ةيئاوشعلا ماقرلاا ديلوتل ةيرامعم ميمصت ايدام اهذيفنتو ليعامسإ نيدلا رخف دمرس .د دومحم ركش لساب بوساحلا ةسدنه مسق / لصوملا ةعماج تاينورتكللأأ ةسدنه ةيلك صخلملا ا ديلوتل ةممصملا ةيرامعملا و يعيبط عيزوتو مظتنم عيزوتب ةيئاوشعلا ماقرلا عيزوتو يسا عيزوت لا ةقيرط مادختساب ) يليار( ـ ( Box-muller لا مادختساب ايدام اهءانب مت يسكعلا ليوحتلا ةقيرطو ) FPGA . ىلع اهءانب مت تادلوملا .ةرود لك يف دحاو مقر دلوت نا نكمم ةيئاوشعلا ماقرلاا تادلوم نم دحاو يا Xilinx Spartan 3E XC3S500E FPGA . هرادقم ددرتب لمعلل ةبسانم ةممصملا تادلوملا 418.41MHz ىوتسمب ياك عبرم صحف ةطساوب اهرابتخا مت تادلوملا نم اهيلع لوصحلا مت يتلا جئاتنلا ةيمها اهرادقم 5 .بولطملا عيزوتلا تققح يتلاو % Received: 9 – 5 2013 Accepted: 10 – 10 2013 Al-Rafidain Engineering Vol.22 No. 2 March 2014 51

Architectural Design of Random Number Generators and Their Hardware Implementations