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The Fujitsu Digital Annealer (DA) is designed to solve fully connectedquadratic unconstrained binary optimization (QUBO) problems. It is implementedon application-specific CMOS hardware and currently solves problems of up to1024 variables. The DA's algorithm is currently based on simulated annealing;however, it differs from it in its utilization of an efficient parallel-trialscheme and a dynamic escape mechanism. In addition, the DA exploits the massiveparallelization that custom application-specific CMOS hardware allows. Wecompare the performance of the DA to simulated annealing and parallel temperingwith isoenergetic cluster moves on two-dimensional and fully connectedspin-glass problems with bimodal and Gaussian couplings. These represent therespective limits of sparse versus dense problems, as well as high-degeneracyversus low-degeneracy problems. Our results show that the DA currently exhibitsa time-to-solution speedup of roughly two orders of magnitude for fullyconnected spin-glass problems with bimodal or Gaussian couplings, over thesingle-core implementations of simulated annealing and parallel tempering MonteCarlo used in this study. The DA does not appear to exhibit a speedup forsparse two-dimensional spin-glass problems, which we explain on theoreticalgrounds. We also benchmarked an early implementation of the Parallel TemperingDA. Our results suggest an improved scaling over the other algorithms for fullyconnected problems of average difficulty with bimodal disorder. The nextgeneration of the DA is expected to be able to solve fully connected problemsup to 8192 variables in size. This would enable the study of fundamentalphysics problems and industrial applications that were previously inaccessibleusing standard computing hardware or special-purpose quantum annealingmachines.

Physics-Inspired Optimization for Quadratic Unconstrained Problems Using a Digital Annealer