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Large-scale neuromorphic hardware systems typically bear the trade-offbetween detail level and required chip resources. Especially when implementingspike-timing-dependent plasticity, reduction in resources leads to limitationsas compared to floating point precision. By design, a natural modification thatsaves resources would be reducing synaptic weight resolution. In this study, wegive an estimate for the impact of synaptic weight discretization on differentlevels, ranging from random walks of individual weights to computer simulationsof spiking neural networks. The FACETS wafer-scale hardware system offers a4-bit resolution of synaptic weights, which is shown to be sufficient withinthe scope of our network benchmark. Our findings indicate that increasing theresolution may not even be useful in light of further restrictions ofcustomized mixed-signal synapses. In addition, variations due to productionimperfections are investigated and shown to be uncritical in the context of thepresented study. Our results represent a general framework for setting up andconfiguring hardware-constrained synapses. We suggest how weight discretizationcould be considered for other backends dedicated to large-scale simulations.Thus, our proposition of a good hardware verification practice may rise synergyeffects between hardware developers and neuroscientists.

Is a 4-bit synaptic weight resolution enough? - Constraints on enabling spike-timing dependent plasticity in neuromorphic hardware